1. Field of the Invention
The invention relates to a semiconductor memory device. More particularly it relates to the semiconductor memory device including a capacitor with a ferroelectric film and having a structure to prevent a leak current.
2. Description of the Related Art
FIG. 8 shows a semiconductor memory device disclosed in IEEE ISSCC 89, p. 242 which uses a ferroelectric film. A cell transistor used in the semiconductor memory device comprises source/drain regions 804a and 804b and a gate electrode 805 formed on a silicon substrate 801 where an active region is defined by forming a device isolation film 802. In this type of semiconductor, a capacitor is disposed through the intermediary of an insulating film on the cell transistor. A lower electrode 809 of the capacitor is formed as a common drive line connecting each memory cells. A ferroelectric film 810 is formed so as to cover the lower electrode 809. Further, an upper electrode 812 is formed on the ferroelectric film 810. Thus, the capacitor is formed on the region having a flat surface, and the cell transistor and capacitor are connected by a local wiring 817 connecting the upper electrode 812 and source/drain region 804b. However, since the local wiring is disposed flatly in this device, it is not effective for reducing the cell size.
In the meanwhile, as shown in FIG. 9, Japanese Unexamined Patent Publication 4-82265 (1992) discloses another semiconductor memory device which utilizes a ferroelectric film without such a local wiring. A cell transistor used in the semiconductor memory device of this type comprises a device isolation film 902, source/drain regions 904a and 904b and a gate electrode 905 formed on a silicon substrate 901. In the device, an interlayer insulating film 906 is formed on the cell transistor, and a lower electrode 909 of the capacitor and capacitor insulating film 910 are directly formed on the source/drain region 904b of the cell transistor by simultaneous patterning. Further, an interlayer insulating film 913 is laminated on the lower electrode 909 and capacitor insulating film 910. A window is formed throughout a part of the interlayer insulating film 913 and the upper electrode 912 is formed thereon. Thus, the capacitor is formed on the region of which surface has step portions. Therefore, the coverage would be deteriorated when the lower electrode 909 is formed by sputtering. In addition, since the lower electrode 909 is directly formed on the substrate 901, in the process of thermal treatment following the formation of the lower electrode 909 and capacitor insulating film 910, elements comprised of the lower electrode 909 and capacitor insulating film 910 are diffused in the source/drain regions 904a and 904b.
In order to solve these problems, a device shown in FIG. 6 has been proposed. The device is manufactured as follows.
First, a silicon substrate 601 having a device isolation film 602 is oxidized followed by forming a gate electrode 603. In use of the gate electrode 603 as a mask, source/drain regions 604a and 604b are formed to form a cell transistor.
After an interlayer insulating film 606 is formed on the cell transistor, a window 607 is opened and a contact plug 608 is embedded therein. Next, a material for a lower electrode of the capacitor and ferroelectric film are deposited on a contact plug 608, and simultaneously patterned in the desired shape to form a capacitor lower electrode 609 and capacitor insulating film 610. Then, a material for an upper electrode is deposited on the lower electrode 609 and insulating film 610, and patterned in the desired shape to form a capacitor upper electrode 612. Next, after depositing an interlayer insulating film 613 on the capacitor, a window 614 is opened so as to extend to a silicon substrate 601 and a wiring 615 is formed by laminating a wiring material. Thus, the semiconductor device is obtained.
However, the semiconductor having the structure described above requires enough marginal spaces A as shown in FIG. 6 when the upper electrode 612 is formed. If the marginal space A is not wide enough, the upper electrode 612 can not be sufficiently etched at step portions, or the upper electrode 612 is adversely formed on the side wall of the capacitor as shown in FIG. 6. These phenomena may cause concentration of an electric field and increase of leak current generated by uneven intensity of the electric field at the edge portion B of the insulating film 610, and may cause to short at the edge portion C of the lower electrode 609. To the contrary, if the marginal space A is too wide, the size of the upper electrode 612 is reduced, whereby large capacity can not be obtained.
Another semiconductor memory device as shown in FIG. 7 has been proposed. In the device, a cell transistor and a contact plug 708 are formed on the silicon substrate 701 by the same method used for the device shown in FIG. 6. A lower electrode 709 is formed on a contact plug 708, and then a ferroelectric film is deposited and etched in use of a mask with enough matching margins which is larger than a lower electrode 709, thereby forming a capacitor insulating film 710 which entirely covers the lower electrode 709. Then, an upper electrode 712 is formed so as to entirely cover the capacitor insulating film 710 on the capacitor insulating film 710 in the same way. In FIG. 7, a reference numeral 702 denotes a device isolation film; 703 denotes a gate electrode; 704a and 704b denote source/drain regions; 705, 706, 713 and 716 denote insulating films; and 715 denotes a wiring.
However, thus formed semiconductor memory device still has a defect of increasing a leak current because of concentration of electric field or uneven intensity of electric field at the edge portion D of the capacitor insulating film 710, or because of reducing a thickness of the capacitor insulating film 710 formed at the edge portion of the lower electrode 709. In addition, grain is readily grown at the interface E between the interlayer insulating film 706 and capacitor insulating film 710 because the crystallinity of the ferroelectric film is poor at the interface, and therefore the leak current is increased through the grain in accordance with an electric field applied to the interface.